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freescale semiconductor data sheet: technical data document number: mc9s08fl16 rev. 3, 11/2010 ? freescale semiconductor, inc., 2009-2010. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. mc9s08fl16 32-pin sdip 1376-02 32-pin lqfp 873a-03 features: 8-bit s08 central processor unit (cpu) ? up to 20 mhz cpu at 4.5 v to 5.5 v across temperature range of ?40 c to 85 c ? hc08 instruction set with added bgnd instruction ? support for up to 32 interrupt/reset sources on-chip memory ? up to 16 kb flash read/program/erase over full operating voltage and temperature ? up to 1024-byte random-access memory (ram) ? security circuitry to prevent unauthorized access to ram and flash contents power-saving modes ? two low power stop modes; reduced power wait mode ? allows clocks to remain enabled to specific peripherals in stop3 mode clock source options ? oscillator (xosc) ? loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 khz to 39.0625 khz or 1 mhz to 16 mhz ? internal clock source (ics) ? internal clock source module containing a frequency-locked-loop (fll) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies up to 10 mhz system protection ? watchdog computer operating properly (cop) reset with option to run from dedicated 1 khz internal clock source or bus clock ? low-voltage detectionwith reset or interrupt; selectable trip points ? illegal opcode detection with reset ? illegal address detection with reset ? flash block protection development support ? single-wire background debug interface ? breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints). ? on-chip in-circuit emul ator (ice) debug module containing two comparators and nine trigger modes. peripherals ?ipc ? interrupt priority controller to provide hardware based nested interrupt mechanism ? adc ? 12-channel, 8-bit resolution; 2.5 ? s conversion time; automatic compare function; 1.7 mv/ ? c temperature sensor; internal bandgap reference channel; operation in stop; optional hardware trigger; fully functional from 4.5 v to 5.5 v ? tpm ? one 4-channel and one 2-channel timer/pulse-width modulators (tpm) modules; selectable input capture, output compare, or buffered edge- or center-aligned pwm on each channel ? mtim16 ? one 16-bit modulo timer with optional prescaler ?sci ? one serial communications interface module with optional 13-bit break; lin extensions input/output ? 30 gpios including 1 output-only pin and 1 input-only pin package options ? 32-pin sdip ? 32-pin lqfp document number: mc9s08fl16 rev. 3, 11/2010 mc9s08fl16 series covers: mc9s08fl16 and mc9s08fl8
mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 2 revision history to provide the most up-to-date information, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to ve rify you have the latest information available, refer to: http://freescale.com/ the following revision history table summariz es changes contained in this document. rev date description of changes 1 march 18, 2009 initial public release. 2 july 20, 2009 updated section 5.12, ?emc performance .? and corrected figure 1 and ta bl e 1 . corrected default trim value to 31.25 khz. 3 nov. 29, 2010 updated ta bl e 7 . related documentation find the most current versions of all documents at: http://www.freescale.com reference manual (mc9s08fl16rm) contains extensive product informati on including modes of operation, memory, resets and interrupts, register defin ition, port pins, cpu, and all module information. 1 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 system clock distribution . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 parameter classification . . . . . . . . . . . . . . . . . . . 9 5.3 absolute maximum ratings . . . . . . . . . . . . . . . . . 9 5.4 thermal characteristics . . . . . . . . . . . . . . . . . . . 10 5.5 esd protection and latch-up immunity . . . . . . 11 5.6 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 supply current characteristics . . . . . . . . . . . . . 17 5.8 external oscillator (xosc) and ics characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.9 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . 21 5.9.1 control timing . . . . . . . . . . . . . . . . . . . . . 22 5.9.2 tpm module timing . . . . . . . . . . . . . . . . 23 5.10 adc characteristics . . . . . . . . . . . . . . . . . . . . . 24 5.11 flash specifications. . . . . . . . . . . . . . . . . . . . . . 26 5.12 emc performance . . . . . . . . . . . . . . . . . . . . . . . 27 5.12.1radiated emissions. . . . . . . . . . . . . . . . . 27 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 mechanical drawings. . . . . . . . . . . . . . . . . . . . . 28 table of contents
mcu block diagram mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 3 1 mcu block diagram the block diagram, figure 1 , shows the structure of mc9s08fl16 series mcu. figure 1. mc9s08fl16 series block diagram 2-ch timer/pwm module ( tpm2 ) voltage regulator port a 20 mhz internal clock source ( ics ) analog-to-digital converter ( adc ) 12-ch 8-bit 4-ch timer/pwm module ( tpm1 ) adp[11:0] v dd v ss reset serial communications interface ( sci ) txd pta0/adp0 pta1/adp1 pta2/adp2 pta3/adp3 pta4/bkgd/ms pta5/irq/tclk/reset pta6/tpm2ch0 pta7/tpm2ch1 tpm2ch[1:0] irq tpm1ch[3:0] port b ptb0/rxd/adp4 ptb1/txd/adp5 ptb2/adp6 ptb3/adp7 ptb4/tpm1ch0 ptb5/tpm1ch1 ptb6/xtal ptb7/extal port c ptc0/adp8 ptc1/adp9 ptc2/adp10 ptc3/adp11 ptc4 ptc5 ptc6 ptc7 port d ptd0 ptd1 ptd2/tpm1ch2 ptd3/tpm1ch3 ptd4 ptd5 rxd external oscillator extal xtal user flash user ram hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management cop lv d mc9s08fl16 ? 1,024 bytes mc9s08fl16 ? 16,384 bytes irq on-chip ice and debug modue ( dbg ) mc9s08fl8 ? 8,192 bytes mc9s08fl8 ? 768 bytes v refh v refl v dda v ssa note 1. pta4 is output only when used as port pin. 2. pta5 is input only when used as port pin. 16-bit modulo timer ( mtim16 ) tclk interrupt priority source ( xosc ) controller ( ipc )
mc9s08fl16 series data sheet, rev. 3 system clock distribution freescale semiconductor 4 2 system clock distribution mc9s08fl16 series use ics module as clock sources. the ics module can use internal or external clock source as reference to provide up to 20 mh z cpu clock. the output of ics module includes, ? oscout ? xosc output provides external reference clock to adc. ? icsffclk ? ics fixed frequency clock refe rence (around 32.768 khz) provides double of the fixed lock signal to tpms and mtim16. ? icsout ? ics cpu clock provides double of the bus clock which is basic clock reference of peripherals. ? icslclk ? alternate bdc clock provides debug signal to bdc module. the tclk pin is an extra external clock source. wh en tclk is enabled, it can provide alternate clock source to tpms and mtim16. the on-chip 1 khz clock provides clock source of cop module. figure 2. system clock distribution diagram ics cpu ? 2 icsout icsffclk bus clock bdc tpm2 tpm1 icslclk fixed clock (xclk) 1 khz adc flash ram sci xosc extal xtal oscout tclk cop ipc mtim16 ? 2
pin assignments mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 5 3 pin assignments this section shows the pin assignments for the mc9s08fl16 series devices. figure 3. mc9s08fl16 series 32-pin sdip package ptc5 1 2 3 4 5 6 7 8 9 10 32 31 30 29 28 27 26 25 24 23 ptc4 pta5/irq/tclk/reset ptd2/tpm1ch2 pta4/bkgd/ms ptd0 ptd1 v dd v ss ptb7/extal ptc6 ptc7 pta0/adp0 ptd5 pta1/adp1 pta2/adp2 pta3/adp3 pta6/tpm2ch0 pta7/tpm2ch1 ptb0/rxd/adp4 11 12 13 14 15 16 22 21 20 19 18 17 ptb6/xtal ptb5/tpm2ch1 ptd3/tpm1ch3 ptb4/tpm1ch0 ptc3/adp11 ptc2/adp10 ptb1/txd/adp5 ptb2/adp6 ptd4 ptb3/adp7 ptc0/adp8 ptc1/adp9
mc9s08fl16 series data sheet, rev. 3 pin assignments freescale semiconductor 6 figure 4. mc9s08fl16 series 32-pin lqfp package table 1. pin availability by package pin-count pin number <-- lowest priority --> highest 32-sdip 32-lqfp port pin i/o alt 1 i/o alt 2 i/o alt 3 i/o 129ptc5i/o 230ptc4i/o 3 31 pta5 i irq i tclk i reset i 4 32 ptd2 i/o tpm1ch2 i/o 5 1 pta4 o bkgd i ms i 62ptd0i/o 73ptd1i/o 84 v dd i 95 v ss i 10 6 ptb7 i/o extal i 11 7 ptb6 i/o xtal o 12 8 ptb5 i/o tpm1ch1 i/o 13 9 ptd3 i/o tpm1ch3 i/o 14 10 ptb4 i/o tpm1ch0 i/o 15 11 ptc3 i/o adp11 i pta4/bkgd/ms 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 ptd0 ptd1 v dd v ss ptb7/extal ptb6/xtal ptb5/tpm1ch1 pta1/adp1 pta2/adp2 pta3/adp3 pta6/tpm2ch0 pta7/tpm2ch1 ptb0/rxd/adp4 ptb1/txd/adp5 ptb2/adp6 ptd3/tpm1ch3 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ptb4/tpm1ch0 ptc3/adp11 ptc2/adp10 ptc1/adp9 ptc0/adp8 ptb3/adp7 ptd4 ptd2/tpm1ch2 pta5/irq/tclk/reset ptc4 ptc5 ptc6 ptc7 pta0/adp0 ptd5 1 9
pin assignments mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 7 note when an alternative function is first en abled, it is possible to get a spurious edge to the module. user software must clear out any associ ated flags before interrupts are enabled. table 1 illustrates the priority if multiple modules are enabled. the highest priority modul e will have control over the pin. selecting a higher priority pin func tion with a lower priority function already enabled can cause spurious e dges to the lower priority module. disable all modules that share a pin before enabli ng another module. 16 12 ptc2 i/o adp10 i 17 13 ptc1 i/o adp9 i 18 14 ptc0 i/o adp8 i 19 15 ptb3 i/o adp7 i 20 16 ptd4 i/o 21 17 ptb2 i/o adp6 i 22 18 ptb1 i/o txd i/o adp5 i 23 19 ptb0 i/o rxd i adp4 i 24 20 pta7 i/o tpm2ch1 i/o 25 21 pta6 i/o tpm2ch0 i/o 26 22 pta3 i/o adp3 i 27 23 pta2 i/o adp2 i 28 24 pta1 i/o adp1 i 29 25 ptd5 i/o 30 26 pta0 i/o adp0 i 31 27 ptc7 i/o 32 28 ptc6 i/o table 1. pin availability by package pin-count (continued) pin number <-- lowest priority --> highest 32-sdip 32-lqfp port pin i/o alt 1 i/o alt 2 i/o alt 3 i/o
mc9s08fl16 series data sheet, rev. 3 memory map freescale semiconductor 8 4 memory map figure 5 shows the memory map for the mc9s08fl16 se ries. on-chip memory in the mc9s08fl16 series of mcus consists of ra m, flash program memory for nonvolat ile data storage, plus i/o and control/status registers. the regi sters are divided into two groups: ? direct-page registers (0x0000 through 0x003f) ? high-page registers (0x1800 through 0x187f) figure 5. mc9s08fl16 series memory map $0040 $0000 $003f $033f $0340 direct page registers $1800 $187f flash $ffff 8192 bytes unimplemented $17ff $1880 $dfff $e000 ram 768 bytes high page registers unimplemented mc9s08fl8 $0040 $0000 $003f $043f $0440 direct page registers $1800 $187f flash $ffff 16384 bytes unimplemented $17ff $1880 $bfff $c000 ram 1024 bytes high page registers unimplemented mc9s08fl16
electrical characteristics mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 9 5 electrical characteristics 5.1 introduction this section contains el ectrical and timing specifications for the mc9s08fl16 series of microcontrollers available at the time of publication. 5.2 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a better understanding, the following classi fication is used and the parameters are tagged accordingly in the tabl es where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 5.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond th e limits specified in table 3 may affect device reliability or cause permanent damage to the device. for functiona l operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appr opriate logic volta ge level (for instance, either v ss or v dd ) or the programmable pullup resistor associated with the pin is enabled. table 2. parameter classifications p those parameters are guaranteed during produ ction testing on each individual device. c those parameters are achieved by the design charac terization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations.
mc9s08fl16 series data sheet, rev. 3 electrical characteristics freescale semiconductor 10 5.4 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage re gulator circuits, and it is user-determined rather than being controlled by the mcu design. to take p i/o into account in power calc ulations, determine the diff erence between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the diff erence between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in ? c can be obtained from: table 3. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to 5.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?0.3 to v dd +0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins, except for pta5 are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d ? 25 ma storage temperature range t stg ?55 to 150 ? c table 4. thermal characteristics rating symbol value unit operating temperature range (packaged) t a t l to t h ?40 to 85 ? c thermal resistance single-layer board 32-pin sdip ? ja 60 ? c/w 32-pin lqfp 85 thermal resistance four-layer board 32-pin sdip ? ja 35 ? c/w 32-pin lqfp 56
electrical characteristics mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 11 t j = t a + (p d ? ? ja ) eqn. 1 where: t a = ambient temperature, ? c ? ja = package thermal resistance, junction-to-ambient, ? c/w p d = p int ?? p i/o p int = i dd ? v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o far much smaller than p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k ? (t j + 273 ? c) eqn. 2 solving equation 1 and equation 2 for k gives: k = p d ? (t a + 273 ? c) + ? ja ? (p d ) 2 eqn. 3 where k is a constant pertaining to the pa rticular part. k can be determined from equation 3 by measuring p d (at equilibrium) for an known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 5.5 esd protection and latch-up immunity although damage from electrostatic di scharge (esd) is much less comm on on these devices than on early cmos circuits, normal handling preca utions must be taken to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can with stand exposure to reasonable levels of static without suffer ing any permanent damage. during the device qualification, esd stresses were performed for th e human body model (hbm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametr ic and functional testing is perf ormed per the applicable device specification at room temperature fo llowed by hot temperature, unless in structed otherwise in the device specification. table 5. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ? storage capacitance c 100 pf number of pulses per pin ? 3 ? latch-up minimum input voltage limit ? ?2.5 v maximum input voltage limit ? 7.5 v
mc9s08fl16 series data sheet, rev. 3 electrical characteristics freescale semiconductor 12 5.6 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. table 6. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm ? 2000 ? v 2 charge device model (cdm) v cdm ? 500 ? v 3 latch-up current at t a = 85 ? ci lat ? 100 ? ma table 7. dc characteristics num c characteristic symbol condition min. typical 1 max. unit 1 p operating voltage ? ? 4.5 ? 5.5 v 2 c output high voltage all i/o pins, low-drive strength v oh i load = ?2 ma v dd ? 1.5 ? ? v p all i/o pins, high-drive strength i load = ?10 ma v dd ? 1.5 ? ? 3 d output high current max total i oh for all ports i oht ???100ma 4 c output low voltage all i/o pins, low-drive strength v ol i load = 2 ma ? ? 1.5 v p all i/o pins, high-drive strength i load = 10 ma ? ? 1.5 5d output low current max total i ol for all ports i olt ???100ma 6p input high voltage all digital inputs v ih ?0.65 ? v dd ??v 7p input low voltage all digital inputs v il ???0.35 ? v dd v 8c input hysteresis all digital inputs v hys ?0.06 ? v dd ??mv 9p input leakage current all input only pins (per pin) |i in |v in = v dd or v ss ?0.1 1 ? a 10 p hi-z (off-state) leakage current all input/output (per pin) |i oz |v in = v dd or v ss ?0.1 1 ? a 11a c pullup, pulldown resistors all digital inputs, when enabled (all i/o pins other than pta5/irq/tclk/reset ) r pu, r pd ? 17.5 36.5 52.5 k ? 11b c pullup, pulldown resistors (pta5/irq/tclk/reset ) r pu, r pd (note 2 ) ? 17.5 36.5 52.5 k ?
electrical characteristics mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 13 12 c dc injection current 3, 4, 5 single pin limit i ic v in < v ss , v in > v dd ?0.2 ? 0.2 ma total mcu limit, includes sum of all stressed pins ?5 ? 5 ma 13 c input capacitance, all pins c in ???8pf 14 c ram retention voltage v ram ??0.61.0v 15 c por re-arm voltage 6 v por ? 0.9 1.4 2.0 v 16 d por re-arm time t por ?10?? ? s 17 p low-voltage detection threshold ? high range v dd falling v dd rising v lv d 1 7 ? 3.9 4.0 4.0 4.1 4.1 4.2 v 18 c low-voltage warning threshold ? high range 1 v dd falling v dd rising v lv w 3 ? 4.5 4.6 4.6 4.7 4.7 4.8 v p low-voltage warning threshold ? high range 0 v dd falling v dd rising v lv w 2 7 ? 4.2 4.3 4.3 4.4 4.4 4.5 v 19 c low-voltage inhibit reset/recover hysteresis v hys ? ? 100 ? mv 20 c bandgap voltage reference 8 v bg ? ? 1.21 ? v 1 typical values are measured at 25 ? c. characterized, not tested. 2 the specified resistor value is the actual value internal to the device. the pullup or pulldown value may appear higher when measured externally on the pin. 3 all functional non-supply pins, except for pta5 are internally clamped to v ss and v dd . 4 input must be current limited to the value specified. to determ ine the value of the required current-limiting resistor, calcula te resistance values for positive and negative clamp voltages, then use the larger of the two values. 5 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if the positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure that external v dd load will shunt current greater than maximum injection current. this will be the great est risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 6 maximum is highest voltage that por is guaranteed. 7 when v dd is in between the minimun of this pa rameter and 4.5 v, the cpu, ram, lvd and flash are full functional, but the performance of other modules may be reduced. 8 factory trimmed at v dd = 5.0 v, temp = 25 ? c table 7. dc characteristics (continued) num c characteristic symbol condition min. typical 1 max. unit
mc9s08fl16 series data sheet, rev. 3 electrical characteristics freescale semiconductor 14 figure 6. typical i oh vs v dd ?v oh (v dd = 5.0 v) (high drive) typical i oh vs. v dd -v oh v dd = 5 v (high drive) 0.000 5.000 10.000 15.000 20.000 25.000 30.000 35.000 40.000 45.000 50.000 0 0.3 0.5 0.8 1 1.3 2 v ma -40c 0c 25c 55c 85c
electrical characteristics mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 15 figure 7. typical i oh vs v dd ?v oh (v dd = 5.0 v) (low drive) typical i oh vs. v dd -v oh v dd = 5v (low drive) 0.000 1.000 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 10.000 0 0.3 0.5 0.8 1 1.3 2 v ma -40c 0c 25c 55c 85c
mc9s08fl16 series data sheet, rev. 3 electrical characteristics freescale semiconductor 16 figure 8. typical i oh vs v ol (v dd = 5.0 v) (high drive) typical i ol vs. v ol v dd = 5 v (high drive) 0.000 5.000 10.000 15.000 20.000 25.000 30.000 35.000 40.000 45.000 50.000 0 0.3 0.5 0.8 1 1.3 2 v ma -40c 0c 25c 55c 85c
electrical characteristics mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 17 figure 9. typical i oh vs v ol (v dd = 5.0 v) (low drive) 5.7 supply current characteristics this section includes information about power supply current in various operating modes. typical i ol vs. v ol v dd = 5v (low drive) 0.000 2.000 4.000 6.000 8.000 10.000 12.000 14.000 0 0.3 0.5 0.8 1 1.3 2 v ma -40c 0c 25c 55c 85c
mc9s08fl16 series data sheet, rev. 3 electrical characteristics freescale semiconductor 18 table 8. supply current characteristics num c parameter symbol bus freq v dd (v) typical 1 1 data in typical column was characterized at 5.0 v, 25 ? c or is typical recommended value. max unit temp 1 p run supply current fei mode, all modules off ri dd 10 mhz 5 5.66 5.75 5.80 ? ma ?40 ? c 25 ? c 85 ? c ?40 ? c 25 ? c 85 ? c p1 mhz 1.61 1.65 1.78 ? 2 c wait mode supply current fei mode, all modules off wi dd 10 mhz 5 2.79 2.86 2.88 ? ? a ?40 ? c 25 ? c 85 ? c ?40 ? c 25 ? c 85 ? c c1 mhz 1.05 1.06 1.06 ? 3 c stop2 mode supply current s2i dd ? 5 1.06 ? ? a ?40 to 85 ? c c stop3 mode supply current no clocks active s3i dd ? 5 1.17 ? ? a ?40 to 85 ? c 4 c adc adder to stop3 ? ? 5 163.88 ? ? a 25 ? c 5c ics adder to stop3 erefsten = 1 ??51.25? ? a 25 ? c 6 c lvd adder to stop3 ? ? 5 161.3 ? ? a 25 ? c
electrical characteristics mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 19 5.8 external oscillator (xosc) and ics characteristics refer to figure 11 for crystal or resonator circuits. table 9. xosc and ics specifications (temperature range = ?40 to 85 ? c ambient) num c characteristic symbol min typical 1 max unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) high range (range = 1) fee or fbe mode 2 high range (range = 1), high gain (hgo = 1), fbelp mode high range (range = 1), low power (hgo = 0), fbelp mode f lo f hi f hi f hi 32 1 1 1 ? ? ? ? 38.4 5 16 8 khz mhz mhz mhz 2 d load capacitors c 1 c 2 see note 3 3d feedback resistor low range (32 khz to 38.4 khz) high range (1 mhz to 16 mhz) r f 10 1 m ? m ? 4d series resistor ? low range low gain (hgo = 0) high gain (hgo = 1) r s ? ? 0 100 ? ? k ? 5d series resistor ? high range low gain (hgo = 0) high gain (hgo = 1) ? 8 mhz 4 mhz 1 mhz r s ? ? ? 0 0 0 0 10 20 k ? 6c crystal startup time 4, 5 low range, low power low range, high power high range, low power high range, high power t cstl t csth ? ? ? ? 200 400 5 15 ? ? ? ? ms 7 t internal reference start-up time t irst ? 60 100 ? s 8d square wave input clock frequency (erefs = 0, erclken = 1) fee or fbe mode 2 fbelp mode f extal 0.03125 0 ? ? 5 20 mhz mhz 9 p average internal reference frequency ? trimmed f int_t ? 31.25 ? khz 10 p dco output frequency range ? trimmed 6 low range (drs = 00) f dco_t 16 ? 20 mhz 11 c total deviation of dco out put from trimmed frequency 4 over full voltage and temperature range over fixed voltage and temperature range of 0 to 70 ? c ? f dco_t ? ?1.0 to 0.5 ? 0.5 ?? 2 ?? 1 %f dco 12 c fll acquisition time 4,7 t acquire 1ms
mc9s08fl16 series data sheet, rev. 3 electrical characteristics freescale semiconductor 20 figure 10. typical crystal or resonator circuit 13 c long term jitter of dco output clock (averaged over 2 ms interval) 8 c jitter ? 0.02 0.2 %f dco 1 data in typical column was characterized at 5.0 v, 25 ? c or is typical recommended value. 2 when ics is configured for fee or fbe mode, input clock so urce must be divisible using rdiv to within the range of 31.25 khz to 39.0625 khz. 3 see crystal or resonator manufacturer?s recommendation. 4 this parameter is characterized and not tested on each device. 5 proper pc board layout procedures must be followed to achieve specifications. 6 the resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 7 this specification applies to any time t he fll reference source or reference divider is changed, trim value changed, dmx32 bit is changed, drs bit is changed, or changing from fll disa bled (fbelp, fbilp) to fll enab led (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 8 jitter is the average deviation from the programmed fre quency measured over the specified interval at maximum f bus . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. table 9. xosc and ics specifications (temperature range = ?40 to 85 ? c ambient) (continued) num c characteristic symbol min typical 1 max unit xosc extal xtal crystal or resonator r s c 2 r f c 1
electrical characteristics mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 21 figure 11. deviation of dco output from trimmed frequency (20 mhz, 5.0 v) 5.9 ac characteristics this section describes timing character istics for each peripheral system. tbd -2.00% -1.50% -1.00% -0.50% 0.00% 0.50% 1.00% -60 -40 -20 0 20 40 60 80 100 120 temperature deviation (%)
mc9s08fl16 series data sheet, rev. 3 electrical characteristics freescale semiconductor 22 5.9.1 control timing figure 12. reset timing table 10. control timing num c rating symbol min typical 1 1 typical values are based on characterization data at v dd = 5.0 v, 25 ? c unless otherwise stated. max unit 1d bus frequency (t cyc = 1/f bus )f bus dc ? 10 mhz 2 d internal low power oscillator period t lpo 700 ? 1300 ? s 3d external reset pulse width 2 2 this is the shortest pulse that is guaranteed to be recognized as a reset pin request. t extrst 100 ? ? ns 4 d reset low drive t rstdrv 34 ? t cyc ??ns 5d bkgd/ms setup time after issuing background debug force reset to enter user or bdm modes t mssu 500 ? ? ns 6d bkgd/ms hold time after issuing background debug force reset to enter user or bdm modes 3 3 to enter bdm mode following a por, bkgd/ms must be held low during the power-up and for a hold time of t msh after v dd rises above v lv d . t msh 100 ? ? ? s 7d irq pulse width asynchronous path 2 synchronous path 4 4 this is the minimum pulse width that is guaranteed to pass th rough the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized. t ilih, t ihil 100 1.5 ? t cyc ? ? ? ? ns 8d keyboard interrupt pulse width asynchronous path 2 synchronous path 4 t ilih, t ihil 100 1.5 ? t cyc ? ? ? ? ns 9c port rise and fall time ? low output drive (ptxds = 0) (load = 50 pf) 5 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 5 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 ? c to 85 ? c. t rise , t fall ? ? 16 23 ? ? ns port rise and fall time ? high output drive (ptxds = 1) (load = 50 pf) 5 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 5 9 ? ? ns t extrst reset pin
electrical characteristics mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 23 figure 13. irq /kbipx timing 5.9.2 tpm module timing synchronizer circuits determine the s hortest input pulses that can be re cognized or the fastest clock that can be used as the optional external source to the timer counter. these synchr onizers operate from the current bus rate clock. figure 14. timer external clock figure 15. timer input capture pulse table 11. tpm input timing no. c function symbol min max unit 1 d external clock frequency f tclk 0f bus /4 hz 2 d external clock period t tclk 4?t cyc 3 d external clock high time t clkh 1.5 ? t cyc 4 d external clock low time t clkl 1.5 ? t cyc 5 d input capture pulse width t icpw 1.5 ? t cyc t ihil kbipx t ilih irq /kbipx t tclk t clkh t clkl tclk t icpw tpmchn t icpw tpmchn
mc9s08fl16 series data sheet, rev. 3 electrical characteristics freescale semiconductor 24 5.10 adc characteristics figure 16. adc input impedance equivalency diagram table 12. 8-bit adc operating conditions characteristic conditions symb min typical 1 1 typical values assume v dda = 5.0 v, temp = 25 ? c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit comment supply voltage absolute v dda 4.5 ? 5.5 v delta to v dd (v dd ? v dda ) 2 2 dc potential difference. ? v dda ?100 0 100 mv ground voltage delta to v ss (v ss ? v ssa ) 2 ? v ssa ?100 0 100 mv input voltage ? v adin v refl ?v refh v input capacitance ?c adin ?4.55.5pf input resistance ? r adin ?3 5k ? analog source resistance 8-bit mode (all valid f adck )r as ??10k ? external to mcu adc conversion clock frequency high speed (adlpc = 0) f adck 0.4 ? 8.0 mhz low power (adlpc = 1) 0.4 ? 4.0 + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
electrical characteristics mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 25 table 13. 8-bit adc characteristics (v refh = v dda , v refl = v ssa ) c characteristic conditions symb min typ 1 max unit comment t supply current adlpc=1 adlsmp=1 adco=1 i dda ?133? ? a t supply current adlpc=1 adlsmp=0 adco=1 i dda ?218? ? a t supply current adlpc=0 adlsmp=1 adco=1 i dda ?327? ? a p supply current adlpc=0 adlsmp=0 adco=1 i dda ?0.582 1 ma c supply current stop, reset, module off i dda ?0.011 1 ? a p adc asynchronous clock source high speed (adlpc = 0) f adack 23.35 mhz t adack = 1/f adack low power (adlpc = 1) 1.25 2 3.3 p conversion time (including sample time) short sample (adlsmp = 0) t adc ?20? adck cycles see reference manual for conversion time variances long sample (adlsmp = 1) ? 40 ? p sample time short sample (adlsmp = 0) t ads ?3.5? adck cycles long sample (adlsmp = 1) ? 23.5 ? d temp sensor slope ?40 ? c? 25 ? c m ?3.266? mv/ ? c 25 ? c? 125 ? c?3.638? d temp sensor voltage 25 ? cv temp25 ?1.396? mv p to t a l unadjusted error 8-bit mode e tue ? ? 0.5 ? 1.0 lsb 2 includes quantization p differential non-linearity 8-bit mode 3 dnl ? ? 0.3 ? 0.5 lsb 2 t integral non-linearity 8-bit mode inl ? ? 0.3 ? 0.5 lsb 2 p zero-scale error 8-bit mode e zs ? ? 0.5 ? 0.5 lsb 2 v adin = v ssa t full-scale error 8-bit mode e fs ? ? 0.5 ? 0.5 lsb 2 v adin = v dda
mc9s08fl16 series data sheet, rev. 3 electrical characteristics freescale semiconductor 26 5.11 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power s ources other than the normal v dd supply. for more detailed information about progra m/erase operations, see the memory section. d quantization error 8-bit mode e q ?? ? 0.5 lsb 2 d input leakage error 8-bit mode e il ? ? 0.1 ? 1 lsb 2 pad leakage 2 * r as 1 typical values assume v dda = 5.0 v, temp = 25 ? c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 based on input pad leakage current. refer to pad electricals. table 14. flash characteristics c characteristic symbol min typical max unit d supply voltage for program/erase ?40 ? c to 85 ? cv prog/erase 4.5 ? 5.5 v d supply voltage for read operation v read 4.5 ? 5.5 v d internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 ? 200 khz d internal fclk period (1/fclk) t fcyc 5?6.67 ? s p byte program time (random location) 2 t prog 9t fcyc p byte program time (burst mode) 2 t burst 4t fcyc p page erase time 2 2 these values are hardware state machine controlled. user c ode does not need to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc p mass erase time 2 t mass 20,000 t fcyc byte program current 3 3 the program and erase currents are additional to the standard run i dd . these values are measured at room temperatures with v dd = 5.0 v, bus frequency = 4.0 mhz. ri ddbp ?4?ma page erase current 3 ri ddpe ?6?ma c program/erase endurance 4 t l to t h = ?40 ? c to 85 ? c t = 25 ? c 4 typical endurance for flash was evaluated for this product family on th e 9s12dx64. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . ? 10,000 ? cycles c data retention 5 t d_ret 5 100 ? years table 13. 8-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) c characteristic conditions symb min typ 1 max unit comment
ordering information mc9s08fl16 series data sheet, rev. 3 freescale semiconductor 27 5.12 emc performance electromagnetic compatibility (emc) performance is highly dependant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and char acteristics of external components as well as mcu software operation all pl ay a significant role in emc performance. the system designer should consult freescale a pplications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance specifi cally targeted at optimizing emc performance. 5.12.1 radiated emissions microcontroller radiated rf emis sions are measured from 150 khz to 1 ghz using th e tem/gtem cell method in accordance with the iec 61967-2 and sae j1752/3 standards. the measurement is performed with the microcontroller installe d on a custom emc evalua tion board while running specialized emc test software. the radiated emissions fr om the microcontroller are measured in a tem cell in two package orientations (the north and east). the maximum radiated rf emissions of the tested configuration in all or ientations are less than or equal to the reported emissions levels. 6 ordering information this section contains ordering info rmation for mc9s08fl16 se ries devices. see below for an example of the device numbering system. 5 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 ? c using the arrhenius equation. for additional informatio n on how freescale defines typical data retention, please refer to engineering bulletin eb618, typical data retention for nonvolatile memory. table 15. radiated emissions, electric field parameter symbol conditions frequency f osc /f bus level 1 (max) 1 data based on qualification test results. unit radiated emissions, electric field v re_tem v dd = 5.0 v t a = 25 ? c package type 32-pin lqfp 0.15 ? 50 mhz 4 mhz crystal 19 mhz bus 9 db ? v 50 ? 150 mhz 5 150 ? 500 mhz 2 500 ? 1000 mhz 1 iec level n ? sae level 1 ? table 16. device numbering system device number 1 memory available packages 2 flash ram mc9s08fl16 16 kb 1024 32 sdip 32 lqfp mc9s08fl8 8 kb 768
mc9s08fl16 series data sheet, rev. 3 package information freescale semiconductor 28 example of the device numbering system: 7 package information 7.1 mechanical drawings the following pages are me chanical drawings for th e packages described in table 17 . 1 see the reference manual, mc9s08fl16 series reference manual , for a complete description of modules in cluded on each device. 2 see ta b l e 1 7 for package information. table 17. package descriptions pin count package type abbreviation designator case no. document no. 32 low quad flat package lqfp lc 873a-03 98ash70029a 32 shrink dual in-line package sdip bm 1376-02 98asa99330d mc temperature range family memory status core (c =?40 ? c to 85 ? c) (9 = flash-based) 9 s08 xx (mc = fully qualified) package designator (see ta b l e 1 7 ) approximate flash size in kb fl 16 c

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